IDWT 5x3: generalize SSE2 version for AVX2
Thanks to our macros that abstract SSE use, the functions can use AVX2 when available (at compile time) This brings an extra 23% speed improvement on bench_dwt in 64bit builds with AVX2 compared to SSE2.
This commit is contained in:
Even Rouault
parent
f6e3475cc9
commit
fd0dc535ad
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@ -52,6 +52,9 @@
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#ifdef __SSSE3__
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#include <tmmintrin.h>
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#endif
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#ifdef __AVX2__
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#include <immintrin.h>
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#endif
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#if defined(__GNUC__)
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#pragma GCC poison malloc calloc realloc free
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@ -63,7 +66,16 @@
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#define OPJ_WS(i) v->mem[(i)*2]
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#define OPJ_WD(i) v->mem[(1+(i)*2)]
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#define PARALLEL_COLS_53 8
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#ifdef __AVX2__
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/** Number of int32 values in a AVX2 register */
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#define VREG_INT_COUNT 8
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#else
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/** Number of int32 values in a SSE2 register */
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#define VREG_INT_COUNT 4
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#endif
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/** Number of columns that we can process in parallel in the vertical pass */
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#define PARALLEL_COLS_53 (2*VREG_INT_COUNT)
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/** @name Local data structures */
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/*@{*/
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@ -553,19 +565,55 @@ static void opj_idwt53_h(const opj_dwt_t *dwt,
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#endif
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}
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#if defined(__SSE2__) && !defined(STANDARD_SLOW_VERSION)
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#if (defined(__SSE2__) || defined(__AVX2__)) && !defined(STANDARD_SLOW_VERSION)
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/* Conveniency macros to improve the readabilty of the formulas */
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#define LOADU(x) _mm_loadu_si128((const __m128i*)(x))
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#define STORE(x,y) _mm_store_si128((__m128i*)(x),(y))
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#if __AVX2__
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#define VREG __m256i
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#define LOAD_CST(x) _mm256_set1_epi32(x)
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#define LOAD(x) _mm256_load_si256((const VREG*)(x))
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#define LOADU(x) _mm256_loadu_si256((const VREG*)(x))
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#define STORE(x,y) _mm256_store_si256((VREG*)(x),(y))
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#define STOREU(x,y) _mm256_storeu_si256((VREG*)(x),(y))
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#define ADD(x,y) _mm256_add_epi32((x),(y))
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#define SUB(x,y) _mm256_sub_epi32((x),(y))
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#define SAR(x,y) _mm256_srai_epi32((x),(y))
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#else
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#define VREG __m128i
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#define LOAD_CST(x) _mm_set1_epi32(x)
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#define LOAD(x) _mm_load_si128((const VREG*)(x))
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#define LOADU(x) _mm_loadu_si128((const VREG*)(x))
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#define STORE(x,y) _mm_store_si128((VREG*)(x),(y))
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#define STOREU(x,y) _mm_storeu_si128((VREG*)(x),(y))
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#define ADD(x,y) _mm_add_epi32((x),(y))
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#define ADD3(x,y,z) ADD(ADD(x,y),z)
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#define SUB(x,y) _mm_sub_epi32((x),(y))
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#define SAR(x,y) _mm_srai_epi32((x),(y))
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#endif
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#define ADD3(x,y,z) ADD(ADD(x,y),z)
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/** Vertical inverse 5x3 wavelet transform for 8 columns, when top-most
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* pixel is on even coordinate */
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static void opj_idwt53_v_cas0_8cols_SSE2(
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static
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void opj_idwt53_v_final_memcpy(OPJ_INT32* tiledp_col,
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const OPJ_INT32* tmp,
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OPJ_INT32 len,
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OPJ_INT32 stride)
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{
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OPJ_INT32 i;
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for (i = 0; i < len; ++i) {
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/* A memcpy(&tiledp_col[i * stride + 0],
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&tmp[PARALLEL_COLS_53 * i + 0],
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PARALLEL_COLS_53 * sizeof(OPJ_INT32))
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would do but would be a tiny bit slower.
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We can take here advantage of our knowledge of alignment */
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STOREU(&tiledp_col[i * stride + 0],
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LOAD(&tmp[PARALLEL_COLS_53 * i + 0]));
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STOREU(&tiledp_col[i * stride + VREG_INT_COUNT],
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LOAD(&tmp[PARALLEL_COLS_53 * i + VREG_INT_COUNT]));
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}
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}
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/** Vertical inverse 5x3 wavelet transform for 8 columns in SSE2, or
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* 16 in AVX2, when top-most pixel is on even coordinate */
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static void opj_idwt53_v_cas0_mcols_SSE2_OR_AVX2(
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OPJ_INT32* tmp,
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const OPJ_INT32 sn,
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const OPJ_INT32 len,
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@ -576,17 +624,28 @@ static void opj_idwt53_v_cas0_8cols_SSE2(
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const OPJ_INT32* in_odd = &tiledp_col[sn * stride];
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OPJ_INT32 i, j;
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__m128i d1c_0, d1n_0, s1n_0, s0c_0, s0n_0;
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__m128i d1c_1, d1n_1, s1n_1, s0c_1, s0n_1;
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const __m128i two = _mm_set1_epi32(2);
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VREG d1c_0, d1n_0, s1n_0, s0c_0, s0n_0;
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VREG d1c_1, d1n_1, s1n_1, s0c_1, s0n_1;
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const VREG two = LOAD_CST(2);
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assert(len > 1);
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#if __AVX2__
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assert(PARALLEL_COLS_53 == 16);
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assert(VREG_INT_COUNT == 8);
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#else
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assert(PARALLEL_COLS_53 == 8);
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assert(VREG_INT_COUNT == 4);
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#endif
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/* Note: loads of input even/odd values must be done in a unaligned */
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/* fashion. But stores in tmp can be done with aligned store, since */
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/* the temporary buffer is properly aligned */
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assert((size_t)tmp % (sizeof(OPJ_INT32) * VREG_INT_COUNT) == 0);
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s1n_0 = LOADU(in_even + 0);
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s1n_1 = LOADU(in_even + 4);
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s1n_1 = LOADU(in_even + VREG_INT_COUNT);
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d1n_0 = LOADU(in_odd);
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d1n_1 = LOADU(in_odd + 4);
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d1n_1 = LOADU(in_odd + VREG_INT_COUNT);
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/* s0n = s1n - ((d1n + 1) >> 1); <==> */
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/* s0n = s1n - ((d1n + d1n + 2) >> 2); */
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@ -600,29 +659,29 @@ static void opj_idwt53_v_cas0_8cols_SSE2(
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s0c_1 = s0n_1;
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s1n_0 = LOADU(in_even + j * stride);
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s1n_1 = LOADU(in_even + j * stride + 4);
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s1n_1 = LOADU(in_even + j * stride + VREG_INT_COUNT);
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d1n_0 = LOADU(in_odd + j * stride);
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d1n_1 = LOADU(in_odd + j * stride + 4);
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d1n_1 = LOADU(in_odd + j * stride + VREG_INT_COUNT);
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/*s0n = s1n - ((d1c + d1n + 2) >> 2);*/
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s0n_0 = SUB(s1n_0, SAR(ADD3(d1c_0, d1n_0, two), 2));
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s0n_1 = SUB(s1n_1, SAR(ADD3(d1c_1, d1n_1, two), 2));
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STORE(tmp + PARALLEL_COLS_53 * (i + 0), s0c_0);
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STORE(tmp + PARALLEL_COLS_53 * (i + 0) + 4, s0c_1);
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STORE(tmp + PARALLEL_COLS_53 * (i + 0) + VREG_INT_COUNT, s0c_1);
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/* d1c + ((s0c + s0n) >> 1) */
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STORE(tmp + PARALLEL_COLS_53 * (i + 1) + 0,
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ADD(d1c_0, SAR(ADD(s0c_0, s0n_0), 1)));
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STORE(tmp + PARALLEL_COLS_53 * (i + 1) + 4,
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STORE(tmp + PARALLEL_COLS_53 * (i + 1) + VREG_INT_COUNT,
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ADD(d1c_1, SAR(ADD(s0c_1, s0n_1), 1)));
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}
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STORE(tmp + PARALLEL_COLS_53 * (i + 0) + 0, s0n_0);
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STORE(tmp + PARALLEL_COLS_53 * (i + 0) + 4, s0n_1);
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STORE(tmp + PARALLEL_COLS_53 * (i + 0) + VREG_INT_COUNT, s0n_1);
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if (len & 1) {
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__m128i tmp_len_minus_1;
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VREG tmp_len_minus_1;
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s1n_0 = LOADU(in_even + ((len - 1) / 2) * stride);
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/* tmp_len_minus_1 = s1n - ((d1n + 1) >> 1); */
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tmp_len_minus_1 = SUB(s1n_0, SAR(ADD3(d1n_0, d1n_0, two), 2));
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@ -631,31 +690,30 @@ static void opj_idwt53_v_cas0_8cols_SSE2(
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STORE(tmp + 8 * (len - 2),
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ADD(d1n_0, SAR(ADD(s0n_0, tmp_len_minus_1), 1)));
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s1n_1 = LOADU(in_even + ((len - 1) / 2) * stride + 4);
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s1n_1 = LOADU(in_even + ((len - 1) / 2) * stride + VREG_INT_COUNT);
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/* tmp_len_minus_1 = s1n - ((d1n + 1) >> 1); */
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tmp_len_minus_1 = SUB(s1n_1, SAR(ADD3(d1n_1, d1n_1, two), 2));
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STORE(tmp + PARALLEL_COLS_53 * (len - 1) + 4, tmp_len_minus_1);
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STORE(tmp + PARALLEL_COLS_53 * (len - 1) + VREG_INT_COUNT,
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tmp_len_minus_1);
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/* d1n + ((s0n + tmp_len_minus_1) >> 1) */
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STORE(tmp + PARALLEL_COLS_53 * (len - 2) + 4,
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STORE(tmp + PARALLEL_COLS_53 * (len - 2) + VREG_INT_COUNT,
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ADD(d1n_1, SAR(ADD(s0n_1, tmp_len_minus_1), 1)));
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} else {
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STORE(tmp + PARALLEL_COLS_53 * (len - 1) + 0, ADD(d1n_0, s0n_0));
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STORE(tmp + PARALLEL_COLS_53 * (len - 1) + 4, ADD(d1n_1, s0n_1));
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STORE(tmp + PARALLEL_COLS_53 * (len - 1) + 0,
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ADD(d1n_0, s0n_0));
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STORE(tmp + PARALLEL_COLS_53 * (len - 1) + VREG_INT_COUNT,
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ADD(d1n_1, s0n_1));
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}
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for (i = 0; i < len; ++i) {
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memcpy(&tiledp_col[i * stride],
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&tmp[PARALLEL_COLS_53 * i],
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PARALLEL_COLS_53 * sizeof(OPJ_INT32));
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}
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opj_idwt53_v_final_memcpy(tiledp_col, tmp, len, stride);
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}
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/** Vertical inverse 5x3 wavelet transform for 8 columns, when top-most
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* pixel is on odd coordinate */
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static void opj_idwt53_v_cas1_8cols_SSE2(
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/** Vertical inverse 5x3 wavelet transform for 8 columns in SSE2, or
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* 16 in AVX2, when top-most pixel is on odd coordinate */
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static void opj_idwt53_v_cas1_mcols_SSE2_OR_AVX2(
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OPJ_INT32* tmp,
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const OPJ_INT32 sn,
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const OPJ_INT32 len,
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@ -664,15 +722,26 @@ static void opj_idwt53_v_cas1_8cols_SSE2(
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{
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OPJ_INT32 i, j;
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__m128i s1_0, s2_0, dc_0, dn_0;
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__m128i s1_1, s2_1, dc_1, dn_1;
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const __m128i two = _mm_set1_epi32(2);
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VREG s1_0, s2_0, dc_0, dn_0;
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VREG s1_1, s2_1, dc_1, dn_1;
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const VREG two = LOAD_CST(2);
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const OPJ_INT32* in_even = &tiledp_col[sn * stride];
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const OPJ_INT32* in_odd = &tiledp_col[0];
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assert(len > 2);
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#if __AVX2__
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assert(PARALLEL_COLS_53 == 16);
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assert(VREG_INT_COUNT == 8);
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#else
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assert(PARALLEL_COLS_53 == 8);
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assert(VREG_INT_COUNT == 4);
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#endif
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/* Note: loads of input even/odd values must be done in a unaligned */
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/* fashion. But stores in tmp can be done with aligned store, since */
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/* the temporary buffer is properly aligned */
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assert((size_t)tmp % (sizeof(OPJ_INT32) * VREG_INT_COUNT) == 0);
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s1_0 = LOADU(in_even + stride);
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/* in_odd[0] - ((in_even[0] + s1 + 2) >> 2); */
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@ -680,30 +749,31 @@ static void opj_idwt53_v_cas1_8cols_SSE2(
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SAR(ADD3(LOADU(in_even + 0), s1_0, two), 2));
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STORE(tmp + PARALLEL_COLS_53 * 0, ADD(LOADU(in_even + 0), dc_0));
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s1_1 = LOADU(in_even + stride + 4);
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s1_1 = LOADU(in_even + stride + VREG_INT_COUNT);
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/* in_odd[0] - ((in_even[0] + s1 + 2) >> 2); */
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dc_1 = SUB(LOADU(in_odd + 4),
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SAR(ADD3(LOADU(in_even + 4), s1_1, two), 2));
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STORE(tmp + PARALLEL_COLS_53 * 0 + 4, ADD(LOADU(in_even + 4), dc_1));
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dc_1 = SUB(LOADU(in_odd + VREG_INT_COUNT),
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SAR(ADD3(LOADU(in_even + VREG_INT_COUNT), s1_1, two), 2));
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STORE(tmp + PARALLEL_COLS_53 * 0 + VREG_INT_COUNT,
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ADD(LOADU(in_even + VREG_INT_COUNT), dc_1));
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for (i = 1, j = 1; i < (len - 2 - !(len & 1)); i += 2, j++) {
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s2_0 = LOADU(in_even + (j + 1) * stride);
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s2_1 = LOADU(in_even + (j + 1) * stride + 4);
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s2_1 = LOADU(in_even + (j + 1) * stride + VREG_INT_COUNT);
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/* dn = in_odd[j * stride] - ((s1 + s2 + 2) >> 2); */
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dn_0 = SUB(LOADU(in_odd + j * stride),
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SAR(ADD3(s1_0, s2_0, two), 2));
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dn_1 = SUB(LOADU(in_odd + j * stride + 4),
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dn_1 = SUB(LOADU(in_odd + j * stride + VREG_INT_COUNT),
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SAR(ADD3(s1_1, s2_1, two), 2));
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STORE(tmp + PARALLEL_COLS_53 * i, dc_0);
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STORE(tmp + PARALLEL_COLS_53 * i + 4, dc_1);
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STORE(tmp + PARALLEL_COLS_53 * i + VREG_INT_COUNT, dc_1);
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/* tmp[i + 1] = s1 + ((dn + dc) >> 1); */
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STORE(tmp + PARALLEL_COLS_53 * (i + 1) + 0,
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ADD(s1_0, SAR(ADD(dn_0, dc_0), 1)));
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STORE(tmp + PARALLEL_COLS_53 * (i + 1) + 4,
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STORE(tmp + PARALLEL_COLS_53 * (i + 1) + VREG_INT_COUNT,
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ADD(s1_1, SAR(ADD(dn_1, dc_1), 1)));
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dc_0 = dn_0;
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@ -712,43 +782,44 @@ static void opj_idwt53_v_cas1_8cols_SSE2(
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s1_1 = s2_1;
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}
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STORE(tmp + PARALLEL_COLS_53 * i, dc_0);
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STORE(tmp + PARALLEL_COLS_53 * i + 4, dc_1);
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STORE(tmp + PARALLEL_COLS_53 * i + VREG_INT_COUNT, dc_1);
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if (!(len & 1)) {
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/*dn = in_odd[(len / 2 - 1) * stride] - ((s1 + 1) >> 1); */
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dn_0 = SUB(LOADU(in_odd + (len / 2 - 1) * stride),
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SAR(ADD3(s1_0, s1_0, two), 2));
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dn_1 = SUB(LOADU(in_odd + (len / 2 - 1) * stride + 4),
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dn_1 = SUB(LOADU(in_odd + (len / 2 - 1) * stride + VREG_INT_COUNT),
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SAR(ADD3(s1_1, s1_1, two), 2));
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/* tmp[len - 2] = s1 + ((dn + dc) >> 1); */
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STORE(tmp + PARALLEL_COLS_53 * (len - 2) + 0,
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ADD(s1_0, SAR(ADD(dn_0, dc_0), 1)));
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STORE(tmp + PARALLEL_COLS_53 * (len - 2) + 4,
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STORE(tmp + PARALLEL_COLS_53 * (len - 2) + VREG_INT_COUNT,
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ADD(s1_1, SAR(ADD(dn_1, dc_1), 1)));
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STORE(tmp + PARALLEL_COLS_53 * (len - 1) + 0, dn_0);
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STORE(tmp + PARALLEL_COLS_53 * (len - 1) + 4, dn_1);
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STORE(tmp + PARALLEL_COLS_53 * (len - 1) + VREG_INT_COUNT, dn_1);
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} else {
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STORE(tmp + PARALLEL_COLS_53 * (len - 1) + 0, ADD(s1_0, dc_0));
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STORE(tmp + PARALLEL_COLS_53 * (len - 1) + 4, ADD(s1_1, dc_1));
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STORE(tmp + PARALLEL_COLS_53 * (len - 1) + VREG_INT_COUNT,
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ADD(s1_1, dc_1));
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}
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for (i = 0; i < len; ++i) {
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memcpy(&tiledp_col[i * stride],
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&tmp[PARALLEL_COLS_53 * i],
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PARALLEL_COLS_53 * sizeof(OPJ_INT32));
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}
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opj_idwt53_v_final_memcpy(tiledp_col, tmp, len, stride);
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}
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#undef VREG
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#undef LOAD_CST
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#undef LOADU
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#undef LOAD
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#undef STORE
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#undef STOREU
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#undef ADD
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#undef ADD3
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#undef SUB
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#undef SAR
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#endif /* defined(__SSE2__) && !defined(STANDARD_SLOW_VERSION) */
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#endif /* (defined(__SSE2__) || defined(__AVX2__)) && !defined(STANDARD_SLOW_VERSION) */
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#if !defined(STANDARD_SLOW_VERSION)
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/** Vertical inverse 5x3 wavelet transform for one column, when top-most
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@ -873,11 +944,11 @@ static void opj_idwt53_v(const opj_dwt_t *dwt,
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if (dwt->cas == 0) {
|
||||
/* If len == 1, unmodified value */
|
||||
|
||||
#if __SSE2__
|
||||
#if (defined(__SSE2__) || defined(__AVX2__))
|
||||
if (len > 1 && nb_cols == PARALLEL_COLS_53) {
|
||||
/* Same as below general case, except that thanks to SSE2 */
|
||||
/* we can efficently process 8 columns in parallel */
|
||||
opj_idwt53_v_cas0_8cols_SSE2(dwt->mem, sn, len, tiledp_col, stride);
|
||||
/* Same as below general case, except that thanks to SSE2/AVX2 */
|
||||
/* we can efficently process 8/16 columns in parallel */
|
||||
opj_idwt53_v_cas0_mcols_SSE2_OR_AVX2(dwt->mem, sn, len, tiledp_col, stride);
|
||||
return;
|
||||
}
|
||||
#endif
|
||||
|
|
@ -916,11 +987,11 @@ static void opj_idwt53_v(const opj_dwt_t *dwt,
|
|||
return;
|
||||
}
|
||||
|
||||
#ifdef __SSE2__
|
||||
#if (defined(__SSE2__) || defined(__AVX2__))
|
||||
if (len > 2 && nb_cols == PARALLEL_COLS_53) {
|
||||
/* Same as below general case, except that thanks to SSE2 */
|
||||
/* we can efficently process 8 columns in parallel */
|
||||
opj_idwt53_v_cas1_8cols_SSE2(dwt->mem, sn, len, tiledp_col, stride);
|
||||
/* Same as below general case, except that thanks to SSE2/AVX2 */
|
||||
/* we can efficently process 8/16 columns in parallel */
|
||||
opj_idwt53_v_cas1_mcols_SSE2_OR_AVX2(dwt->mem, sn, len, tiledp_col, stride);
|
||||
return;
|
||||
}
|
||||
#endif
|
||||
|
|
@ -1291,7 +1362,7 @@ static OPJ_BOOL opj_dwt_decode_tile(opj_thread_pool_t* tp,
|
|||
/* since for the vertical pass */
|
||||
/* we process PARALLEL_COLS_53 columns at a time */
|
||||
h_mem_size *= PARALLEL_COLS_53 * sizeof(OPJ_INT32);
|
||||
h.mem = (OPJ_INT32*)opj_aligned_malloc(h_mem_size);
|
||||
h.mem = (OPJ_INT32*)opj_aligned_32_malloc(h_mem_size);
|
||||
if (! h.mem) {
|
||||
/* FIXME event manager error callback */
|
||||
return OPJ_FALSE;
|
||||
|
|
@ -1348,7 +1419,7 @@ static OPJ_BOOL opj_dwt_decode_tile(opj_thread_pool_t* tp,
|
|||
if (j == (num_jobs - 1U)) { /* this will take care of the overflow */
|
||||
job->max_j = rh;
|
||||
}
|
||||
job->h.mem = (OPJ_INT32*)opj_aligned_malloc(h_mem_size);
|
||||
job->h.mem = (OPJ_INT32*)opj_aligned_32_malloc(h_mem_size);
|
||||
if (!job->h.mem) {
|
||||
/* FIXME event manager error callback */
|
||||
opj_thread_pool_wait_completion(tp, 0);
|
||||
|
|
@ -1403,7 +1474,7 @@ static OPJ_BOOL opj_dwt_decode_tile(opj_thread_pool_t* tp,
|
|||
if (j == (num_jobs - 1U)) { /* this will take care of the overflow */
|
||||
job->max_j = rw;
|
||||
}
|
||||
job->v.mem = (OPJ_INT32*)opj_aligned_malloc(h_mem_size);
|
||||
job->v.mem = (OPJ_INT32*)opj_aligned_32_malloc(h_mem_size);
|
||||
if (!job->v.mem) {
|
||||
/* FIXME event manager error callback */
|
||||
opj_thread_pool_wait_completion(tp, 0);
|
||||
|
|
|
|||
|
|
@ -213,6 +213,15 @@ void * opj_aligned_realloc(void *ptr, size_t size)
|
|||
return opj_aligned_realloc_n(ptr, 16U, size);
|
||||
}
|
||||
|
||||
void *opj_aligned_32_malloc(size_t size)
|
||||
{
|
||||
return opj_aligned_alloc_n(32U, size);
|
||||
}
|
||||
void * opj_aligned_32_realloc(void *ptr, size_t size)
|
||||
{
|
||||
return opj_aligned_realloc_n(ptr, 32U, size);
|
||||
}
|
||||
|
||||
void opj_aligned_free(void* ptr)
|
||||
{
|
||||
#if defined(OPJ_HAVE_POSIX_MEMALIGN) || defined(OPJ_HAVE_MEMALIGN)
|
||||
|
|
|
|||
|
|
@ -71,6 +71,14 @@ void * opj_aligned_malloc(size_t size);
|
|||
void * opj_aligned_realloc(void *ptr, size_t size);
|
||||
void opj_aligned_free(void* ptr);
|
||||
|
||||
/**
|
||||
Allocate memory aligned to a 32 byte boundary
|
||||
@param size Bytes to allocate
|
||||
@return Returns a void pointer to the allocated space, or NULL if there is insufficient memory available
|
||||
*/
|
||||
void * opj_aligned_32_malloc(size_t size);
|
||||
void * opj_aligned_32_realloc(void *ptr, size_t size);
|
||||
|
||||
/**
|
||||
Reallocate memory blocks.
|
||||
@param m Pointer to previously allocated memory block
|
||||
|
|
|
|||
Loading…
Reference in New Issue