Improve memory clearing in JIT.
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325908279e
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106d9d3a25
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@ -3048,13 +3048,50 @@ else
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static SLJIT_INLINE void reset_fast_fail(compiler_common *common)
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{
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DEFINE_COMPILER;
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sljit_s32 size = common->fast_fail_end_ptr - common->fast_fail_start_ptr;
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sljit_s32 src = SLJIT_IMM;
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sljit_s32 i;
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struct sljit_label *loop;
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SLJIT_ASSERT(common->fast_fail_start_ptr < common->fast_fail_end_ptr);
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OP2(SLJIT_SUB, TMP1, 0, STR_PTR, 0, SLJIT_IMM, IN_UCHARS(1));
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for (i = common->fast_fail_start_ptr; i < common->fast_fail_end_ptr; i += sizeof(sljit_sw))
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OP1(SLJIT_MOV, SLJIT_MEM1(SLJIT_SP), i, TMP1, 0);
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if (size == sizeof(sljit_sw))
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{
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OP1(SLJIT_MOV, SLJIT_MEM1(SLJIT_SP), common->fast_fail_start_ptr, SLJIT_IMM, 0);
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return;
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}
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if (sljit_get_register_index(TMP3) >= 0 && !sljit_has_cpu_feature(SLJIT_HAS_ZERO_REGISTER))
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{
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OP1(SLJIT_MOV, TMP3, 0, SLJIT_IMM, 0);
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src = TMP3;
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}
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if (size <= 6 * sizeof(sljit_sw))
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{
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for (i = common->fast_fail_start_ptr; i < common->fast_fail_end_ptr; i += sizeof(sljit_sw))
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OP1(SLJIT_MOV, SLJIT_MEM1(SLJIT_SP), i, src, 0);
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return;
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}
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GET_LOCAL_BASE(TMP1, 0, common->fast_fail_start_ptr);
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i = ((size / (sljit_s32)sizeof(sljit_sw)) % 3) * sizeof(sljit_sw);
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OP2(SLJIT_ADD, TMP2, 0, TMP1, 0, SLJIT_IMM, size - i);
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loop = LABEL();
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OP1(SLJIT_MOV, SLJIT_MEM1(TMP1), 0, src, 0);
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OP2(SLJIT_ADD, TMP1, 0, TMP1, 0, SLJIT_IMM, 3 * sizeof(sljit_sw));
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OP1(SLJIT_MOV, SLJIT_MEM1(TMP1), -2 * (sljit_sw)sizeof(sljit_sw), src, 0);
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OP1(SLJIT_MOV, SLJIT_MEM1(TMP1), -1 * (sljit_sw)sizeof(sljit_sw), src, 0);
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CMPTO(SLJIT_LESS, TMP1, 0, TMP2, 0, loop);
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if (i >= (sljit_sw)sizeof(sljit_sw))
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OP1(SLJIT_MOV, SLJIT_MEM1(TMP1), 0, src, 0);
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if (i >= 2 * (sljit_sw)sizeof(sljit_sw))
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OP1(SLJIT_MOV, SLJIT_MEM1(TMP1), sizeof(sljit_sw), src, 0);
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}
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static SLJIT_INLINE void do_reset_match(compiler_common *common, int length)
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@ -571,12 +571,14 @@ static SLJIT_INLINE sljit_uw sljit_get_generated_code_size(struct sljit_compiler
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#define SLJIT_HAS_FPU 0
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/* [Limitation] Some registers are virtual registers. */
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#define SLJIT_HAS_VIRTUAL_REGISTERS 1
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/* [Emulated] Has zero register (setting a memory location to zero is efficient). */
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#define SLJIT_HAS_ZERO_REGISTER 2
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/* [Emulated] Count leading zero is supported. */
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#define SLJIT_HAS_CLZ 2
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#define SLJIT_HAS_CLZ 3
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/* [Emulated] Conditional move is supported. */
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#define SLJIT_HAS_CMOV 3
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#define SLJIT_HAS_CMOV 4
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/* [Emulated] Conditional move is supported. */
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#define SLJIT_HAS_PREFETCH 4
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#define SLJIT_HAS_PREFETCH 5
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#if (defined SLJIT_CONFIG_X86 && SLJIT_CONFIG_X86)
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/* [Not emulated] SSE2 support is available on x86. */
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@ -684,6 +684,8 @@ SLJIT_API_FUNC_ATTRIBUTE sljit_s32 sljit_has_cpu_feature(sljit_s32 feature_type)
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#else
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#error "FIR check is not implemented for this architecture"
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#endif
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case SLJIT_HAS_ZERO_REGISTER:
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return 1;
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#if (defined SLJIT_MIPS_REV && SLJIT_MIPS_REV >= 1)
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case SLJIT_HAS_CLZ:
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@ -626,6 +626,8 @@ SLJIT_API_FUNC_ATTRIBUTE sljit_s32 sljit_has_cpu_feature(sljit_s32 feature_type)
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return 1;
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#endif
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/* A saved register is set to a zero value. */
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case SLJIT_HAS_ZERO_REGISTER:
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case SLJIT_HAS_CLZ:
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case SLJIT_HAS_PREFETCH:
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return 1;
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@ -451,6 +451,9 @@ SLJIT_API_FUNC_ATTRIBUTE sljit_s32 sljit_has_cpu_feature(sljit_s32 feature_type)
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return 1;
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#endif
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case SLJIT_HAS_ZERO_REGISTER:
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return 1;
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#if (defined SLJIT_CONFIG_SPARC_64 && SLJIT_CONFIG_SPARC_64)
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case SLJIT_HAS_CMOV:
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return 1;
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@ -2316,6 +2316,10 @@ SLJIT_API_FUNC_ATTRIBUTE sljit_s32 sljit_emit_op2(struct sljit_compiler *compile
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if (!HAS_FLAGS(op)) {
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if ((src2 & SLJIT_IMM) && emit_lea_binary(compiler, dst, dstw, src1, src1w, SLJIT_IMM, -src2w) != SLJIT_ERR_UNSUPPORTED)
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return compiler->error;
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if (SLOW_IS_REG(dst) && src2 == dst) {
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FAIL_IF(emit_non_cum_binary(compiler, BINARY_OPCODE(SUB), dst, 0, dst, 0, src1, src1w));
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return emit_unary(compiler, NEG_rm, dst, 0, dst, 0);
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}
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}
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if (dst == SLJIT_UNUSED)
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